The present invention relates in general to semiconductor memories and in particular to dynamic memory circuits with improved refresh mechanism.
Memory cells in dynamic semiconductor memories such as a dynamic random access memory (DRAM) store data on a capacitive element. Due to charge leakage from the capacitive element memory cells must be refreshed periodically. The refresh process typically involves performing a read operation to bring the level of charge stored in the memory cells back to their original state. Different types of refresh methods have been developed over time. According to one refresh method commonly referred to as auto refresh, the refresh timer is external to the memory chip and the memory chip performs a refresh operation in response to a periodic refresh command supplied by a controller. According to another refresh method referred to as self refresh, the refresh timer is internal to the memory chip and all the memory chip requires is a refresh start command from the controller. Typically, memory cells that are being refreshed are not accessible for normal read and write operations.
With current technology, DRAM memory cells need to be refreshed every 64 ms. This 64 ms refresh period developed as an industry standard and is based on the data retention capability of the DRAM cell technology. Simultaneously refreshing all rows in a typical memory chip will not only cause a big surge in power requirements, it will also cause all data accesses to stall, which adversely impacts performance. To avoid these problems, refresh operations are typically staggered between banks of memory and according to the number of rows in 4096 (4K) or 8192 (8K) cycles. A DRAM being refreshed in 8K cycles, would therefore need a refresh command every 7.8 μs (64 ms/8192). This is commonly referred to as the periodic refresh interval tREFI. The time it takes to complete a single refresh operation after which an active cycle can begin (i.e., minimum time to activate and precharge a word line during a refresh operation), typically referred to as tRFC, is preferably a small fraction of the periodic refresh interval tREFI to maximize the time for normal read and write operation.
This type of multi-bank, time division approach to refreshing DRAMs has thus far been effective in addressing the power and performance tradeoffs associated with the refresh operation. As the memory cell density of DRAM devices increases, however, either longer refresh times or a larger number of refresh operations, or both will be required. This is so because the number of memory cells in a row (or page) that are refreshed simultaneously every tREFI (e.g., 7.8 μs) increases with total memory capacity. For example, a 512M synchronous DRAM with an 8K refresh cycle must refresh a page of 64K (512M/8K) cells simultaneously. This is significantly larger than the typical page size that is activated during normal mode of operation (e.g., 16K for 512M DDR2 DRAM) and presents a heavy power load for the circuit.
One way to address the power management problem associated with the refresh operation in higher density DRAMs is to increase the refresh-to-active cycle time tRFC. A typical refresh-to-active cycle time tRFC for a 256M synchronous DRAM maybe in the range of 75 ns, while tRFC for a 2G synchronous DRAM may reach around 200 ns, and for a 4G DRAM may reach well above 300 ns. Because in a memory bank that is being refreshed, normal memory read/write operations are not allowed during tRFC, longer tRFC reduces time available to the controller for accessing the DRAM. This adversely impacts DRAM performance by reducing the amount of time available for normal read/write operation.
Thus, as the memory cell density increases in dynamic semiconductor memories, the need arises for improved refresh mechanisms that address power requirements without sacrificing time available for normal read/write operations.